When a Rogers PCB core thickness changes, update the physical stackup immediately and review the dielectric model before reusing it. A material family name and one Dk number are not a complete simulation input. The appropriate starting value depends on the ordered construction, frequency, characterization method and the way the solver represents conductors.
The useful outcome is a traceable material-card revision: what changed, which inputs remain provisional and what evidence will qualify the new model. The worksheet below illustrates that process without claiming a measured result or a universal thickness correction.
Recover the conditions behind the existing material card
Open the archived model that produced the original artwork. Record the exact laminate grade, core identifier, dielectric spacing, foil type, finished conductor thickness, line cross-section and any coating. Keep nominal drawing dimensions separate from measured dimensions. A total board thickness is not the same input as the spacing between an RF trace and its reference plane.
Then record the Dk source and revision, frequency range, axis or anisotropy settings, loss model, roughness model and solver version. Identify whether the entry came from a manufacturer document, a software library or an extraction from your own coupon. Preserve the original entry so the previous design remains reproducible.
Use the Dk and Df test-method guide to distinguish the quantities. In particular, the effective permittivity of a microstrip mode includes its field distribution in the substrate and surrounding region. It is not automatically the bulk dielectric input that an electromagnetic solver expects.
Read the product’s conditions and thickness notes
For RO4350B, the RO4000 data sheet gives process Dk 3.48 ± 0.05 (10 GHz, 23°C, clamped stripline) and Design Dk 3.66 (8–40 GHz, differential phase length). Design Dk averages tested lots and common thicknesses. The 4 mil exception, 3.33 ± 0.05, is process Dk.
Its LoPro notes specify approximately 0.0007 inch added per core and a roughly 0.1 Design Dk reduction from 0.020 to 0.004 inch. Do not generalize this into a universal thickness correction. Confirm the ordered construction and the fabricator’s definition of finished dielectric spacing.
For a different example, the RO3003G2 data sheet lists process Dk of 3.00 ± 0.04 at 10 GHz and 23°C, and Design Dk of 3.07 at 77 GHz. It also describes the design value as an average over lots and common thicknesses. The RO3003G2 reference provides product context, but neither those two numbers nor a thickness ratio supplies a frequency conversion formula.
The source revisions reviewed here are RO4000 revision 1592 080322 and RO3003G2 revision 1625 102522. Record the revision used for your actual order and obtain construction-specific guidance when the published conditions do not cover it.
Separate a geometry change from a dielectric change
Consider a hypothetical RO4350B microstrip study over 8–12 GHz. Change the nominal dielectric spacing from 20 mil to 10 mil while retaining the same specified foil construction. For this screening exercise, use 0.508 mm and 0.254 mm for those spacings, a 1.00 mm initial trace width and 0.035 mm finished copper thickness. These are assumed dimensions, not a validated impedance design.
| Model case | Spacing h | Width w | w/h | Copper t/h |
|---|---|---|---|---|
| Old geometry | 0.508 mm | 1.00 mm | 1.969 | 0.0689 |
| New core, unchanged width | 0.254 mm | 1.00 mm | 3.937 | 0.1378 |
| New core, half width | 0.254 mm | 0.50 mm | 1.969 | 0.1378 |
Halving the width restores w/h, but does not restore t/h. Gaps, solder-mask dimensions, surface texture and launch geometry also require separate treatment. Therefore, matching one ratio does not establish equal impedance, phase delay or loss. Let the field solver evaluate the changed structure before attributing a response difference to Dk.
Run a geometry-only comparison first, keeping the same provisional dielectric assumptions. Then vary dielectric and conductor assumptions in separately labeled studies. This makes each result interpretable and avoids tuning several unrelated inputs until one curve happens to match.
Keep copper effects consistent with the model
Rogers’ technical discussion of circuit materials and phase velocity, on pages 24–25 of the May 2019 collection, shows that copper roughness can affect the Dk inferred from circuit measurements. Conductor effects become more influential on thinner constructions. Its numerical examples are specific to the materials and circuits tested; they are not correction factors for this worksheet.
Before combining a circuit-derived Design Dk with an explicit roughness treatment, check the solver’s material definition and the characterization assumptions. If both already account for the same conductor-induced phase effect, the combination can count it twice. Do not automatically remove the roughness model or substitute process Dk. Resolve the convention with the model provider and correlate the complete model. The copper-foil roughness guide helps organize the required foil information.
Issue a provisional revision with an explicit release condition
For the hypothetical thickness change, the following record keeps a nominal starting point separate from qualification. Retaining 3.66 for an initial comparison does not certify that it is the best correlated value for the thinner construction.
| Record field | Archived revision A | Provisional revision B |
|---|---|---|
| Construction | 20 mil core; saved foil and fabrication drawing | 10 mil core; foil identity and finished spacing to be confirmed |
| Dielectric input | Design Dk 3.66; retain original source and settings | Start at 3.66 for geometry comparison; request data for the revised construction |
| Source record | Archived PDF revision and library version | Current PDF revision, supplier response and solver convention |
| Correlation evidence | Retain any original coupon data without relabeling it | New geometry measurements and calibrated coupon data required |
| Release condition | Preserve the original approval scope | Meet project phase, impedance and loss limits over the operating band |
Do not convert a process-Dk tolerance into a guaranteed Design-Dk tolerance. Where uncertainty remains, document its basis and run sensitivity cases separately from specification limits. If those cases change the design decision, resolve the missing input before releasing artwork.
Correlate the revision without concealing dimensional errors
Rogers’ explanation of differential phase length uses nearby microstrip lines that differ in length while sharing other construction details. It emphasizes matching launch arrangements and measurement limitations. Follow a documented extraction method rather than treating a raw transmission phase difference as dielectric Dk.
Before fitting a value, verify actual dielectric spacing, etched width and profile, finished copper and any coating. Record calibration, reference planes and connector assembly. Use the connector-launch transfer checklist when the thinner core also changes the transition.
Compare phase, impedance and attenuation across the required band. Check another line length or structure that was not used for fitting. Archive residual differences, measurement uncertainty and the acceptance limits. A fit that requires an implausible dielectric change should trigger a geometry or fixture review, not an undocumented library overwrite.
Review the dielectric data for your revised core
Bring old and new thicknesses, foil constructions, material-card values, source revisions, frequency range and available coupon measurements. Include the stackup drawings and solver settings so the review can distinguish missing dielectric data from changed geometry. Request a material and stackup review, or collect the fabrication requirements in the RFQ checklist builder.